1. Field of the Invention
This invention relates to a method for reusing electronic hardware component designs as a part of other designs.
2. Description of the Related Technology
A design methodology and a design environment for a hardware/software system co-design environment has been disclosed previously in EP-A-772140 describing a hardware/software co-design environment and design methodology based on a data-model that allows to specify, simulate, and synthesize heterogeneous hardware/software architectures from a heterogeneous specification. Said environment and said methodology are based on the principle of encapsulation of existing hardware and software compilers and allow for the interactive synthesis of hardware/software and hardware/hardware interfaces. Said database is compiled on a memory structure adapted for access by executable programs on a computer for generating the implementation of said heterogeneous essentially digital system, comprising a plurality of objects representing aspects of said digital system wherein said objects comprise primitive objects representing the specification of said digital system and hierarchical objects being created by said executable programs while generating the implementation of said digital system, said hierarchical objects being refinements of said primitive objects and having more detail and preserving any one or all of said aspects to thereby generate said implementation of said digital system; and further comprising relations inbetween said primitive objects and inbetween said hierarchical objects and between said primitive objects and said hierarchical objects; and further comprising functions for manipulating said objects and said relations. This type of design environment and method, disclosed in EP-A-772140, uses objects that represent aspects of the digital system. This type of design environment needs functions for manipulating the objects, in order to achieve an implementation of the digital system. These functions and the executable programs compiled on a computer refine the primitive objects and give rise to the implementation. The present patent application as well as EP-A-867820 on the other hand disclose another type of design environment and design methodology. EP-A-867820 is incorporated herein by reference. The present patent application discloses a design environment and design methodology that faces another problem, as summarised herebelow.
The rush forward of digital implementation technology faces contemporary chip designers with ever increasing design complexities. This makes the ability to reuse components in a system an essential design skill. Examples of such components are embedded cores, or complex random logic blocks. The established view on reuse is focused at the structural level. A component is made reusable by matching it to a standard interface. This interface defines input/output signals, their timing relationship etc. Such an interface allows to hide the detailed design of a component as intellectual property (IP) of a designer, and yet makes the component available for reuse. The reuse of hardware components at the structural level is not without problems. Several reasons are mentioned for this:                Reuse is in the first place a matter of reusing functionality, not structure. It happens often that a component can be ‘almost’ reused, but requires additional encapsulation to match the right behavior. For instance, a digital filter can have the ideal characteristic and performance for a modem system, but contains a serial coefficient programming input instead of the required parallel one.        Structural reuse seals the behavior of a component in a closed box behind the reuse interface. As a result, the reused behavior can only be manipulated indirectly through this interface. Introducing for instance a wait state in the operation of a memory controller might require cumbersome interface manipulations.        Current hardware development environments are good in capturing, simulation and synthesis of hardware components. They do however a bad job in manipulating the same descriptions. As an example, VHDL defines a component as an entity with a well defined port set. It is not possible to strip the ports of an entity depending on some external design condition.        
As shown in table 1, the difficulties of reusing structure can be substantial. The table shows some statistics for a DECT transceiver. It lists the total number of blocks, and the amount of blocks that have a programming interface function (prog). The RT-VHDL line count is shown, first without this programming function (wo/prog) and next including it (w/prog). It clearly shows the extra RT coding required by one extra per-block function.
TABLE 1RT counts for DECT designBlock countRT-VHDL line countTotalprogwo/progw/progDECT252317K28K
This situation has been recognized by other authors as a ‘Silicon Ceiling’ (G. Martin. Design methodologies for system level ip. In Proc. DATE 1998, pages 286-302). Research solutions have been either to encapsulate VHDL within an advanced design environment (G. Lehmann, B. Wunder, and K. Muller-Glaser. A vhdl reuse workbench. In Proc. EDAC 1996, pages 412-417) or else to extend the semantics of VHDL itself (P. Ashenden, P. Wilsey, and D. Martin. Reuse through genericity in suave. In Proc. VIUF 1997 Fall Conf., pages 170-177 and B. Djafri and J. Benzakki. Oovhdl: Object oriented vhdl. In Proc. VIUF 1997 Fall Conf., pages 54-59).
Aims of the Invention
A primary aim of the present invention is to provide a method for reusing complete electronic hardware component designs in other hardware designs.
A further aim of the present invention is to provide a method enabling reuse the function of an electronic hardware component in another design.
Another aim of the present invention is to provide a method enabling reuse of at least a part of the functionality of an electronic hardware component design.